The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a strip level substrate and method for manufacturing a semiconductor package using the same capable of minimizing an early warpage phenomenon of a strip level substrate.
A sheet of wafer is provided with several hundred or several thousand chips on which the same electrical circuits are printed. However, the printed chips cannot transfer or receive external electrical signals, and further, the chips having fine circuits are easily damaged by external shocks. Therefore, there is a need for a semiconductor package in which the chips are electrically connected, more resistant to external shocks, and sealed and packaged to suit the desired physical function and shape.
Generally, the semiconductor package is manufactured in various structures using various materials, such as a lead frame made of metal, a resin-based printed circuit board on which predetermined circuit paths are integrated or a circuit film, etc.
Use of semiconductor is found in almost all electrical products due to advancement of the electronic industry, and as such various package sizes and shapes are in need. In particular, light-weight, highly-integrated semiconductor chips with rapid processing speed and the packages having right size and shape are especially in need for small electronic devices and mobile products.
Therefore, a recent trend in the industry uses substrates having chip attaching regions in a matrix arrangement structure for improving productivity per unit time. The substrate is subject to a chip attaching process, a wire boding process, and a molding process, etc., and then a sawing or singulation process, etc., which separates the substrate into pieces thereby allowing the contemporaneous manufacture of a plurality of semiconductor packages.
For example, a plurality of semiconductor packages in general are manufactured simultaneously by attaching a semiconductor chip to each unit substrate of a strip level substrate including a plurality of unit substrates, and then performing a wire boding process between the semiconductor chip and the unit substrate while simultaneously performing a molding process, and subsequently sawing them at the unit level.
A conventional semiconductor package is subject to a process to apply and then pattern solder resists on the front surface of the strip level substrate at the time of manufacturing thereof and to expose the electrode terminals and ball lands in each unit substrate.
However, although the facile nature of the process is advantageous, during the process for manufacturing the package, the solder resist applied on the front surface of the strip level substrate repeatedly expands and contracts during the reflow process, causing an early warpage phenomenon on the strip level substrate. As a result, the progress of the process thereafter becomes more difficult and the unit level semiconductor package degrades.
Such a problem also occurs in a flip chip package during the manufacture of a semiconductor package by applying a solder resist on the electrode terminal of a strip level substrate, progressing the reflow and then forming a bump.
Therefore, in order to secure the reliability of a semiconductor package, there has been need for a strip level substrate capable of preventing an early warpage phenomenon.